Hardware trojans have long been a concern for digital circuit designers. The trojans can be introduced in a number of ways, including through circuit designs submitted by third parties for implementation in integrated circuits (ICs) or field programmable gate arrays (FPGAs). Using third parties for portions of digital circuit design saves designers valuable time, particularly with respect to designs for Ethernet control or cryptographic cores. Essentially, instead of wasting time re-programming something that is already well-known, the designer can focus on the unique aspects of the digital circuit design and then insert the designs from the third parties where needed.
However, because the software designer has not developed the third-party design, the exact layout and design provided to the designer from the third party is unknown. In some cases, these purchased designs contain nodes outside of the path from the terminal inputs to the terminal outputs, wherein such nodes are referred to as dangling nodes. Sometimes these dangling nodes are placed purposefully to distribute heat within a circuit generated through use of the third-party design. In other situations, dangling nodes are the result of poor design, where the dangling nodes are left in the design because it is easier than removing them (since they have no impact on the functionality of the circuit). Or sometimes, the dangling nodes are intentionally placed by a malicious designer, and are designed to facilitate leakage trojans (e.g., leak sensitive data).
Detecting these hardware trojans has long been a topic of research. Existing methods of mitigating the hardware trojans include attempting to identify all trojans and removing them from the circuit, but in general there is no guarantee that all of the trojans have been found. Therefore, there is a need for an efficient, effective method for preventing inclusion of hardware trojans in ICs and/or FPGAs.